ASICs
You have a creative idea for your product?Contact us! We cast your idea into silicon and deliver the finished product ready for series production. Everything from one source - from the first presentation to the taped IC.
We presently use the following processes for Analog-, Mixed-Signal-, and Digital-Full-Custom-ASICs:
1.5 µm BiCMOS (SPDM) 50V DMOS (optional) |
0.6 µm BiCMOS (DPDM) embedded EEPROM (optional) |
0,25 µm CMOS (2P5M, emb. Flash) |
0.5 µm CMOS (SPTM) |
1.5 µm Bipolar (DM) |
5 µm Bipolar (DM) |
0,8 µm CMOS (1PDM) |
Wafer test and chip packaging
We are able to test in our test laboratories 2"- 8" - wafers under high temperatures and either ink or carry out wafer mapping simultaneously.
Thereafter, the tested chips are packaged in one of the many current package variations.
| MLP | : MLP-QUAD| MLP-DUAL | MLP-MICRO |
| ARRAY | : SSBGA | SSLGA | FTBGA | CBGA |
| MICRO | : SOT66x | SC70 | SC79 | SOT23 | SOT143 | TSOT | SOD323 | TO92 |
| POWER | : TO220 | DDPAK | SOT223 |
| SOP | : SOIC | QSOP | SSOP | MSOP| TSSOP |
| QFP | : MQFP | LQFP | TQFP |
| PDIP | : PDIP |
| PLCC | : PLCC |
After final testing of the finished chips taping and visual inspection will be carried out, depending on customers’ requirements.
Your ASIC – from the idea to the series product – everything from one source.